// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:14 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_irq_gen.v
//
//  Interrupt Request generation
//
//  Original Author: Ameer Youssef 
//  Current Owner: Ameer Youssef   
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_irq_gen.v $
//    $DateTime: 2015/05/27 13:06:10 $
//    $Revision: #5 $
//
////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen
  #(parameter WIDTH = 1,
    parameter FALLING_EDGE = 0,
    parameter ANY_EDGE = 0,
    parameter ASYNC_D = 0) (
output reg              irq,
input  wire             rst,
input  wire             clk,
input  wire             sclr,
input  wire             en,
input  wire [WIDTH-1:0] d
);

// -------------------------
// Registers and nets
// -------------------------

reg  [WIDTH-1:0] d_s1;
wire [WIDTH-1:0] d_s1_nxt;
reg  [WIDTH-1:0] d_s2;

genvar i;

generate
if (ASYNC_D==1) begin: mux_gen
  for (i = 0; i < WIDTH; i = i + 1) begin: mux_di_gen
    dwc_e12mp_phy_x4_ns_gen_mux mux (
      .out (d_s1_nxt[i]),
      .sel (en),
      .d0  (d_s1[i]),
      .d1  (d[i])
    );
  end
end
else begin: no_mux_gen
  assign d_s1_nxt = en ? d : d_s1;
end
endgenerate

// Delay d when enabled, otherwise hold
always @(posedge clk or posedge rst) begin
  if (rst) begin
    d_s1 <= {WIDTH{1'b0}};
    d_s2 <= {WIDTH{1'b0}};
  end
  else begin
    d_s1 <= d_s1_nxt;
    d_s2 <= d_s1;
  end
end

// Generate interrupt request (sticky, with sync clear)
generate
if (FALLING_EDGE==1) begin: falling_edge
  always @(posedge clk or posedge rst)
    if (rst)
      irq <= 1'b0;
    else begin
      if (sclr)
        irq <= 1'b0;
      else // falling edge
        irq <= irq | ((d_s1=={WIDTH{1'b0}}) & (d_s2=={WIDTH{1'b1}}));
    end
end
else if (ANY_EDGE==1) begin: any_edge
  always @(posedge clk or posedge rst)
    if (rst)
      irq <= 1'b0;
    else begin
      if (sclr)
        irq <= 1'b0;
      else // any edge
        irq <= irq | (d_s1 != d_s2);
    end
end
else begin: rising_edge
  always @(posedge clk or posedge rst)
    if (rst)
      irq <= 1'b0;
    else begin
      if (sclr)
        irq <= 1'b0;
      else // rising edge
        irq <= irq | ((d_s1=={WIDTH{1'b1}}) & (d_s2=={WIDTH{1'b0}}));
    end
end
endgenerate

endmodule

